1. Field of the Invention
The present invention relates to a semiconductor device comprising an N-type metal oxide semiconductor field effect transistor (MOSFET) and a P-type MOSFET both containing high dielectric constant films.
2. Description of the Related Art
In recent years, the utilization of a thin film having high dielectric constant called high-k as a component material for semiconductor devices is actively investigated. Typical high-k materials include oxides of elements such as Zr, Hf and the like. The use of such materials for a gate insulating film of a MOSFET reduces a silicon oxide-conversion electrical thickness, even though the physical thickness of the gate insulating film is increased to a certain level, thereby providing physically and structurally stable gate insulating films. Thus, both or either one of an increase of metal oxide semiconductor (MOS) capacity for enhancing MOSFET characteristics and a reduction of a gate leakage current as compared with a conventional case of employing silicon oxide can be achieved.
Japanese Laid-open patent publication No. 2002-280,461 discloses a complementary metal oxide semiconductor (CMOS) device including an N-MOSFET and P-MOSFET employing such high-k material. The N-MOSFET and P-MOSFET include a gate insulating film composed of a low dielectric constant film such as silicon oxide and the like, and a high dielectric constant film and a gate electrode composed of polycrystalline silicon. The gate electrode is disposed so as to contact with the high dielectric constant film of the gate insulating film.
However, a comprehension is obtained according to the recent study, in which a phenomenon called Fermi level pinning is caused when the gate insulating film is composed of a high-k film and the gate electrode is composed of a polycrystalline silicon (C. Hobbs et al., entitled “Fermi Level Pinning at the Poly Si/Metal Oxide Interface”, 2003 Symposium on VLSI Technology Digest of Technical Papers, 4-89114-035-6/03). It is considered that Fermi level pinning is caused when an energy level is created on the basis of chemical bonding of silicon with the above-described metal for composing the high-dielectric constant film diffusing through the polycrystalline silicon that composes the gate electrode, in vicinity of an interface on the side of the gate insulating film in the gate electrode.
When the metal composing the high dielectric constant film is diffused in the polycrystalline silicon of the gate electrode of the MOSFET, a depletion layer is created in the gate polycrystalline silicon in vicinity of an interface thereof with the gate insulating film. Sufficient electrical field cannot be applied to the gate insulating film due to an influence of such depletion layer even though a gate voltage is applied, and thus it is difficult to induce enough amount of carrier in the channel region. As a result, a problem is arisen, in which a threshold voltage is increased, and further a fluctuation in the threshold voltage is also increased.
Such Fermi level pinning is easy to be occurred in a P-type MOSFET that includes a gate electrode composed of a polycrystalline silicon containing P-type impurity, in particular in a case of employing Hf and/or Zr for the high dielectric constant film.
In the meantime, high dielectric constant films having same composition and same film thickness are employed for gate insulating films of N-type MOSFET and P-type MOSFET, which respectively constitute internal circuits of LSI in conventional CMOS devices. In such case, a problem is occurred that the gate leakage current generated in the N-type MOSFET is higher than that generated in the P-type MOSFET in the CMOS device. Therefore, the gate leakage current in the N-type MOSFET is focused in view of power consumption design, and a high dielectric constant film having a suitable film thickness, which is capable of sufficiently reducing the gate leakage current to an acceptable level, is deposited.
On the other hand, a threshold voltage for the P-type MOSFET employing a high dielectric constant film containing a specific element such as Hf, Zr and the like is increased to a level that is higher than that for the P-type MOSFET employing silicon oxide for the gate insulating film, for the reason stated above, and is eventually increased to a level that provides a difficult situation in establishing a desired threshold voltage by adjusting density of an impurity in the Si substrate.